In telecom PLL's output clock signals are divided down from a high frequency clock by programmable dividers. Multiple programmable dividers can be connected to the same high frequency clock. In order to align multiple programmable dividers outputs aligned with other and with the central phase of the PLL filter, some alignment method needs to used. In prior art solutions clock counters in the programmable dividers were overloaded regularly with known values from the programmable divider drivers. Wide busses were required to each programmable divider.